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 INTEGRATED CIRCUITS
DATA SHEET
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* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4508B MSI Dual 4-bit latch
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Dual 4-bit latch
DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outputs provided EO is LOW. Changing the ST input to the LOW state locks the
HEF4508B MSI
data into the latch. A HIGH on the reset line forces the outputs to a LOW level regardless of the state of the ST input. The 3-state outputs are controlled by the output-enable input. A HIGH on EO causes the outputs to assume a high impedance OFF-state regardless of other input conditions. This allows the outputs to interface directly with bus orientated systems. When EO is LOW the contents of the latches are available at the outputs.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
Dual 4-bit latch
HEF4508B MSI
Fig.2 Pinning diagram.
HEF4508BP(N): HEF4508BD(F): HEF4508BT(D):
24-lead DIL; plastic (SOT101-1) 24-lead DIL; ceramic (cerdip) (SOT94) 24-lead SO; plastic (SOT137-1)
( ): Package Designator North America PINNING D0A to D3A, D0B to D3B STA , STB MRA, MRB EOA, EOB O0A to O3A, O0B to O3B FUNCTION TABLE INPUTS MR L L L H X Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial Z = high impedance OFF state ST H H L X X EO L L L L H Dn H L X X X OUTPUT On H L latched L Z data inputs strobe inputs master reset inputs output enable inputs 3-state outputs
January 1995
3
Philips Semiconductors
Product specification
Dual 4-bit latch
HEF4508B MSI
Fig.3 Logic diagram (one 4-bit latch).
January 1995
4
Philips Semiconductors
Product specification
Dual 4-bit latch
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns; see also waveforms Fig.4. VDD V Propagation delays ST On HIGH to LOW 5 10 15 5 LOW to HIGH Dn On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR On HIGH to LOW Output transition times HIGH to LOW 10 15 5 10 15 5 10 15 5 LOW to HIGH 3-state propagation delays Output enable times EO On HIGH 5 10 15 5 LOW Output disable times EO On HIGH 5 10 15 5 LOW 10 15 January 1995 5 tPLZ tPHZ 35 20 18 45 20 18 70 40 36 90 40 36 ns ns ns ns ns ns 10 15 tPZL tPZH 45 20 18 45 20 18 90 40 36 90 40 36 ns ns ns ns ns ns 10 15 tTLH tTHL tPHL tPLH tPHL tPLH tPHL 115 50 35 115 50 35 95 40 30 95 40 30 100 40 30 60 30 20 60 30 20 230 100 70 230 100 70 190 80 60 190 80 60 200 80 60 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX.
HEF4508B MSI
TYPICAL EXTRAPOLATION FORMULA 88 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 88 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
Philips Semiconductors
Product specification
Dual 4-bit latch
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Minimum ST pulse width; HIGH Minimum MR pulse width; HIGH Recovery time for MR Set-up times Dn ST Hold times Dn ST 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 thold tsu tRMR tWMRH tWSTH SYMBOL MIN. TYP. 50 30 20 40 24 20 20 20 15 35 25 20 20 20 15 25 15 10 20 12 10 0 0 0 10 5 0 0 0 0 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
HEF4508B MSI
see also waveforms Fig.4
VDD V Dynamic power dissipation per package (P) 5 10 15
TYPICAL FORMULA FOR P (W) 2 000 fi + (foCL) x VDD2 9 000 fi + (foCL) x 25 000 fi + (foCL) x VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
6
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Dual 4-bit latch HEF4508B MSI
Philips Semiconductors
Product specification
Dual 4-bit latch
APPLICATION INFORMATION Some examples of application for the HEF4508B are: * Buffer storage * Holding registers * Data storage and multiplexing
HEF4508B MSI
Fig.5 Example of a bus register using HEF4508B and HEF4015B.
January 1995
8
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Dual 4-bit latch HEF4508B MSI


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